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| IDTTM InterpriseTM Integrated Communications Processor 79RC32438 Features 32-bit CPU Core - MIPS32 instruction set - Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches - 16 dual-entry JTLB with variable page sizes - 3-entry instruction TLB - 3-entry data TLB - Max issue rate of one 32x16 multiply per clock - Max issue rate of one 32x32 multiply every other clock - CPU control with start, stop and single stepping - Software breakpoints support - Hardware breakpoints on virtual addresses - Enhanced JTAG and ICE Interface that is compatible with v2.5 of the EJTAG Specification DDR Memory Controller - Supports up to 2GB of DDR SDRAM - 2 chip selects (each chip select supports 4 internal DDR banks) - Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices - Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR SDRAM devices - Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs - Automatic refresh generation Memory and Peripheral Device Controller - Provides "glueless" interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices - Demultiplexed address and data buses: 16-bit data bus, 26-bit address bus, 6 chip selects, supports alternate bus masters, control for external data bus buffers - Supports 8-bit and 16-bit width devices Automatic byte gathering and scattering - Flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/postwrite delay (0 to 31), supports external wait state generation, supports Intel and Motorola style peripherals - Write protect capability per chip select - Programmable bus transaction timer generates warm reset when counter expires - Supports up to 64 MB of memory per chip select Counter/Timers - Three general purpose 32-bit counter timers PCI Interface - 32-bit PCI revision 2.2 compliant (3.3V only) - Supports host or satellite operation in both master and target modes - Support for synchronous and asynchronous operation - PCI clock supports frequencies from 16 MHz to 66 MHz - PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitration - I2O "like" PCI Messaging Unit Block Diagram MII MII MIPS-32 CPU Core ICE EJTAG D. Cache MMU I. Cache Interrupt Controller : : 2 Ethernet 10/100 Interfaces 3 Counter Timers IPBusTM On-Chip Memory DMA Controller DDR DDR & Device Controllers I2C Controller 2 UARTS (16550) Arbiter GPIO Interface SPI Controller PCI Master/Target Interface PCI Arbiter (Host Mode) Memory & Peripheral Bus I2C Bus Ch. 1 Ch. 2 Serial Channels GPIO Pins SPI Bus PCI Bus IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 59 (c) 2004 Integrated Device Technology, Inc. May 25, 2004 DSC 6148 IDT 79RC32438 DMA Controller - 10 DMA channels: two channels for PCI (PCI to Memory and Memory to PCI), two for each Ethernet interface, two channels for memory to memory operations, two channels for external operations - Provides flexible descriptor based operation - Supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length. Two Ethernet Interfaces - 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant - Two IEEE 802.3u compatible Media Independent Interfaces (MII) with serial management interface - MII supports IEEE 802.3u auto-negotiation speed selection - Supports 64 entry hash table based multicast address filtering - 512 byte transmit and receive FIFOs - Supports flow control functions outlined in IEEE Std. 802.3x1997 Universal Asynchronous Receiver Transmitter (UART) - Compatible with the 16550 and 16450 UARTs - Two completely separate serial channels - Modem control functions (CTS, RTS, DSR, DTR, RI, DCD) - 16-byte transmit and receive buffers - Programmable baud rate generator derived from the system clock - Fully programmable serial characteristics: - 5, 6, 7, or 8 bit characters - Even, odd or no parity bit generation and detection - 1, 1-1/2 or 2 stop bit generation - Line break generation and detection - False start bit detection - Internal loopback mode 2 I C-Bus - Supports standard 100 Kbps mode as well as 400 Kbps fast mode - Supports 7-bit and 10-bit addressing - Supports four modes: master transmitter, master receiver, slave transmitter, slave receiver Additional General Purpose Peripherals - Two 16550-compatible serial ports - Interrupt controller - System integrity functions - General purpose I/O controller - Serial peripheral interface (SPI) On-chip Memory - 4KB of high speed SRAM organized as 1K x 32 bits - Supports burst and non-burst byte, halfword, triple-byte, and word CPU, PCI, and DMA accesses Debug Support - Rev. 2.6 compliant EJTAG Interface memory with minimal CPU intervention using a highly sophisticated direct memory access (DMA) engine. All data transfers through the RC32438 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module. CPU Execution Core The 32-bit CPU core is 100% compatible with the MIPS32 instruction set architecture (ISA). Specifically, this device features the 4Kc CPU core developed by MIPS Technologies Inc. (www.mips.com). This core issues a single instruction per cycle, includes a five stage pipeline, and is optimized for applications that require integer arithmetic. The CPU core includes 16 KB instruction and 16 KB data caches. Both caches are 4-way set associative and can be locked on a per line basis, which allows the programmer control over this precious on-chip memory resource. The core also features a memory management unit (MMU). The CPU core also incorporates an enhanced joint test access group (EJTAG) interface that is used to interface to in-circuit emulator tools, providing access to internal registers and enabling the part to be controlled externally, simplifying the system debug process. The use of this core allows IDT's customers to leverage the broad range of software and development tools available for the MIPS architecture, including operating systems, compilers, and in-circuit emulators. Double Data Rate Memory Controller The RC32438 incorporates a high performance double data rate (DDR) memory controller which supports both x16 and x32 memory configurations up to 2GB. This module provides all of the signals required to interface to both memory modules and discrete devices, including two chip selects, differential clocking outputs and data strobes. Memory and I/O Controller The RC32438 uses a dedicated local memory/IO controller including a de-multiplexed 16-bit data and 26-bit address bus. It includes all of the signals required to interface directly to as many as six Intel or Motorolastyle external peripherals, and the interface can be configured to support both 8-bit and 16-bit peripherals. DMA Controller The DMA controller consists of 10 independent DMA channels, all of which operate in exactly the same manner. The DMA controller off-loads the CPU core from moving data among the on-chip interfaces, external peripherals, and memory. The controller supports scatter/gather DMA with no alignment restrictions, appropriate for communications and graphics systems. PCI Interface The PCI interface on the RC32438 is compatible with version 2.2 of the PCI specification. An on-chip arbiter supports up to six external bus masters, supporting both fixed priority and rotating priority arbitration schemes. The part can support both satellite and host PCI configurations, enabling the RC32438 to act as a slave controller for a PCI add-in Device Overview The RC32438 is a member of the IDTTM InterpriseTM family of PCI integrated communications processors. It incorporates a high performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main 2 of 59 May 25, 2004 IDT 79RC32438 card application, or as the primary PCI controller in the system. The PCI interface can be operated synchronously or asynchronously to the other I/O interfaces on the RC32438 device. Ethernet Interface The RC32438 has two Ethernet Channels supporting 10Mbps and 100Mbps speeds to provide a standard media independent interface (MII) off-chip, allowing a wide range of external devices to be connected efficiently. UART Interface The RC32438 contains two completely separate serial channels (UARTs) that are compatible with the industry standard 16550 UART. System Integrity Functions The RC32438 contains a programmable watchdog timer that generates NMI when the counter expires and an address space monitor that reports errors in response to accesses to undecoded address regions. General Purpose I/O Controller The RC32438 contains 32 general purpose input/output pins. Each pin may be used as an active high or active low level interrupt or nonmaskable interrupt input, and each signal may be used as a bit input or output port. I2C Interface The standard I2C interface allows the RC32438 to connect to a number of standard external peripherals for a more complete system solution. The RC32438 supports both master and slave operations. Debug Support The RC32438 supports the industry standard Rev. 2.6 EJTAG interface. February 4, 2003: Revised description for EJTAG/JTAG pins in Table 1. Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal Timing, as part of EJTAG description. March 4, 2003: In Table 2, removed "pull-up" from PCI pin category and from GPIO [24] and GPIO[30-26]. In Table 20, changed max. values for VccSI/O, VccCore, and VccPLL. July 9, 2003: In Table 7: changed values for DDRDATA, DDRDM, and DDRADDR--WEN signals, and deleted old footnote #3 and changed values in new footnote #3. In Table 8, changed Tdo values. Changed Figure 7. Changed values in Table 18, Power Consumption. Removed IPBus Monitor feature which included changes to Tables 1, 2, 21, 24, and 25. Deleted Table 13 which resulted in a re-ordering of subsequent tables. March 8, 2004: Added 300MHz speed grade. May 25, 2004: In Table 9, signals MIIxRXCLK and MIIxTXCLK, the Min and Max values for Thigh/Tlow_9c were changed to 140 and 260 respectively and the Min and Max values for Thigh/Tlow_9d were changed to 14.0 and 26.0 respectively. Thermal Considerations The RC32438 consumes less than 2.7 W peak power. It is guaranteed in a ambient temperature range of 0 to +70 C for commercial temperature devices and - 40 to +85 for industrial temperature devices. Revision History November 7, 2002: Initial publication. Preliminary Information. November 15, 2002: Added footnotes to Tables 5, 9, and 10. December 12, 2002: Added Clock Speed parameter to PLL and Core supply in Table 16. December 19, 2002: Release version. January 13, 2003: Changed Thermal Considerations to read less than 2.7W instead of 2.5W, added values to CLK parameter in Table 5, and revised EJTAG description. 3 of 59 May 25, 2004 IDT 79RC32438 Pin Description Table The following table lists the functions of the pins provided on the RC32438. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. Signal System CLK Type Name/Description I Master Clock. This is the master clock input. The processor frequency is a multiple of this clock frequency. This clock is used as the system clock for all memory and peripheral bus operations. External Clock. This clock is used for all memory and peripheral bus operations. Cold Reset. The assertion of this signal initiates a cold reset. This causes the processor state to be initialized, boot configuration to be loaded, and the internal PLL to lock onto the master clock (CLK). Reset. The assertion of this bidirectional signal initiates a warm reset. This signal is asserted by the RC32438 during a warm reset. EXTCLK COLDRSTN O I RSTN I/O Memory and Peripheral Bus BDIRN O External Buffer Direction. Memory and peripheral bus external data bus buffer direction control. If the RC32438 memory and peripheral bus is connected to the A side of a transceiver, such as an IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of the transceiver. Bus Grant. This signal is asserted by the RC32438 to indicate that the RC32438 has relinquished ownership of the memory and peripheral bus. External Buffer Enable. This signal provides an output enable control for an external buffer on the memory and peripheral data bus. Bus Request. This signal is asserted by an external device to request ownership of the memory and peripheral bus. Byte Write Enables. These signals are memory and peripheral bus byte write enable signals. BWEN[0] corresponds to byte lane MDATA[7:0] BWEN[1] corresponds to byte lane MDATA[15:8] Chip Selects. These signals are used to select an external device on the memory and peripheral bus. Address Bus. 22-bit memory and peripheral bus address bus. MADDR[25:22] are available as GPIO alternate functions Data Bus. 16-bit memory and peripheral data bus. During a cold reset, these pins function as inputs that are used to load the boot configuration vector. Output Enable. This signal is asserted when data should be driven on by an external device on the memory and peripheral bus. Read Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from an external device. A low level indicates a write to an external device. Table 1 Pin Description (Part 1 of 9) BGN BOEN BRN BWEN[1:0] O O I O CSN[5:0] MADDR[21:0] MDATA[15:0] OEN RWN O O I/O O O 4 of 59 May 25, 2004 IDT 79RC32438 Signal WAITACKN Type I Name/Description Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE O O O O DDR Address Bus. 14-bit multiplexed DDR bus address bus. This bus is used to transfer the addresses to the DDR devices. DDR Bank Address. These signals are used to transfer the bank address to the DDRs. DDR Column Address Strobe. This signal is asserted during DDR transactions. DDR Clock Enable. The DDR clock enable is asserted during normal DDR operation. This signal is negated during following a cold reset or during a power down operation. DDR Negative DDR clock. These signals are the negative clock of the differential DDR clock pair. Two copies of this output are provided to reduce signal loading. DDR Positive DDR clock. These signals are the positive clock of the differential DDR clock pair. Two copies of this output are provided to reduce signal loading. DDR Chip Selects. These active low signals are used to select DDR device(s) on the DDR bus. DDR Data Bus. 32-bit DDR data bus used to transfer data between the RC32438 and the DDR devices. Data is transferred on both edges of the clock. DDR Data Write Enables. Byte data write enables used to enable specific byte lanes during DDR writes. DDRDM[0] corresponds to DDRDATA[7:0] DDRDM[1] corresponds to DDRDATA[15:8] DDRDM[2] corresponds to DDRDATA[23:16] DDRDM[3] corresponds to DDRDATA[31:24] DDRDM[4] corresponds to DDRDATA[39:32] DDRDM[5] corresponds to DDRDATA[47:40] DDRDM[6] corresponds to DDRDATA[55:48] DDRDM[7] corresponds to DDRDATA[54:56] (Refer to the DDR Data Bus Multiplexing section in Chapter 7 of the RC32438 User Reference Manual.) DDR Data Strobes. DDR byte data strobes used to clock data between DDR devices and the RC32438. These strobes are inputs during DDR reads and outputs during DDR writes. DDRDQS[0] corresponds to DDRDATA[7:0]. DDRDQS[1] corresponds to DDRDATA[15:8]. DDRDQS[2] corresponds to DDRDATA[23:16]. DDRDQS[3] corresponds to DDRDATA[31:24]. DDR Bus Switch Output Enables. These pins are used to enable external data bus switches in systems that support data bus multiplexing. DDR Row Address Strobe. The DDR row address strobe is asserted during DDR transactions. Table 1 Pin Description (Part 2 of 9) DDRCKN[1:0] O DDRCKP[1:0] O DDRCSN[1:0] DDRDATA[31:0] DDRDM[7:0] O I/O O DDRDQS[3:0] I/O DDROEN[3:0] DDRRASN O O 5 of 59 May 25, 2004 IDT 79RC32438 Signal DDRVREF DDRWEN PCI Bus PCIAD[31:0] I/O PCI Multiplexed Address/Data Bus. Address is driven by a bus master during initial PCIFRAMEN assertion. Data is then driven by the bus master during writes or by the bus target during reads. PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the bus master during the initial PCIFRAMEN assertion. Byte enable signals are driven by the bus master during subsequent data phase(s). PCI Clock. Clock used for all PCI bus transactions. PCI Device Select. This signal is driven by a bus target to indicate that the target has decoded the address as one of its own address spaces. PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus transaction. Negation indicates the last data. PCI Bus Grant. In PCI host mode with internal arbiter: The assertion of these signals indicates to the agent that the internal RC32438 arbiter has granted the agent access to the PCI bus. In PCI host mode with external arbiter: PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32438 that access to the PCI bus has been granted. PCIGNTN[3:1]: unused and driven high. In PCI satellite mode: PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the RC32438 that access to the PCI bus has been granted. PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used as a PCI Serial EEPROM chip select PCIGNTN[3:2]: unused and driven high. Note: When the GPIO register is programmed in the alternate function mode for bits GPIO [26] and [28], these bits become PCIGNTN [4] and [5] respectively. PCI Initiator Ready. Driven by the bus master to indicate that the current datum can complete. PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring. PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during address and write Data phases. Driven by the bus target during the read data phase. PCI Parity Error. If a parity error is detected, this signal is asserted by the receiving bus agent 2 clocks after the data is received. Table 1 Pin Description (Part 3 of 9) Type I O Name/Description DDR Voltage Reference. SSTL_2 DDR voltage reference generated by an external source. DDR Write Enable. DDR write enable is asserted during DDR write transactions. PCICBEN[3:0] I/O PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] I I/O I/O I/O PCIIRDYN PCILOCKN PCIPAR I/O I/O I/O PCIPERRN I/O 6 of 59 May 25, 2004 IDT 79RC32438 Signal PCIREQN[3:0] Type I/O Name/Description PCI Bus Request. In PCI host mode with internal arbiter: These signals are inputs whose assertion indicates to the internal RC32438 arbiter that an agent desires ownership of the PCI bus. In PCI host mode with external arbiter: PCIREQN[0]: asserted by the RC32438 to request ownership of the PCI bus. PCIREQN[3:1]: unused and driven high. In PCI satellite mode: PCIREQN[0]: this signal is asserted by the RC32438 to request use of the PCI bus. PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during configuration read and write transactions. PCIREQN[3:2]: unused and driven high. Note: When the GPIO register is programmed in the alternate function mode for bits GPIO [24] and [27], these bits become PCIREQN [4] and [5] respectively. PCI Reset. In host mode, this signal is asserted by the RC32438 to generate a PCI reset. In satellite mode, assertion of this signal initiates a warm reset. PCI System Error. This signal is driven by an agent to indicate an address parity error, data parity error during a special cycle command, or any other system error. Requires an external pull-up. PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indicate a retry. PCI Target Ready. Driven by the bus target to indicate that the current data can complete. PCIRSTN PCISERRN I/O I/O PCISTOPN PCITRDYN I/O I/O General Purpose Input/Output GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SOUT Alternate function: UART channel 0 serial output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SINP Alternate function: UART channel 0 serial input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0RIN Alternate function: UART channel 0 ring indicator input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0DCDN Alternate function: UART channel 0 data carrier detect input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0DTRN Alternate function: UART channel 0 data terminal ready input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0DSRN Alternate function: UART channel 0 data set ready input. Table 1 Pin Description (Part 4 of 9) GPIO[1] I/O GPIO[2] I/O GPIO[3] I/O GPIO[4] I/O GPIO[5] I/O 7 of 59 May 25, 2004 IDT 79RC32438 Signal GPIO[6] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0RTSN Alternate function: UART channel 0 request to send output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0CTSN Alternate function: UART channel 0 clear to send input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1SOUT Alternate function: UART channel 1 serial output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1SINP Alternate function: UART channel 1 serial input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1DTRN Alternate function: UART channel 1 data terminal ready output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1DSRN Alternate function: UART channel 1 data set ready input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1RTSN Alternate function: UART channel 1 request to send output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U1CTSN Alternate function: UART channel 1 clear to send input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMAREQN0 Alternate function: External DMA channel 0 request input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMAREQN1 Alternate function: External DMA channel 1 request input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMADONEN0 Alternate function: External DMA channel 0 done input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMADONEN1 Alternate function: External DMA channel 1 done input. Table 1 Pin Description (Part 5 of 9) GPIO[7] I/O GPIO[8] I/O GPIO[9] I/O GPIO[10] I/O GPIO[11] I/O GPIO[12] I/O GPIO[13] I/O GPIO[14] I/O GPIO[15] I/O GPIO[16] I/O GPIO[17] I/O 8 of 59 May 25, 2004 IDT 79RC32438 Signal GPIO[18] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMAFINN0 Alternate function: External DMA channel 0 finished output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMAFINN1 Alternate function: External DMA channel 1 finished output. General Purpose I/O. This pin can be configured as a general purpose I/O pin Alternate function pin name: MADDR[22] Alternate function: Memory and peripheral bus address output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[23] Alternate function: Memory and peripheral bus address output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[24] Alternate function: Memory and peripheral bus address output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[25] Alternate function: Memory and peripheral bus address output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[4] Alternate function: PCI Request 4 input or output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: AFSPARE1 Alternate function: reserved. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[4] Alternate function: PCI Grant 4 output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[5] Alternate function: PCI Request 5 input or output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[5] Alternate function: PCI Grant 5 output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: Reserved Alternate function: Reserved. Table 1 Pin Description (Part 6 of 9) GPIO[19] I/O GPIO[20] I/O GPIO[21] I/O GPIO[22] I/O GPIO[23] I/O GPIO[24] I/O GPIO[25] I/O GPIO[26] I/O GPIO[27] I/O GPIO[28] I/O GPIO[29] I/O 9 of 59 May 25, 2004 IDT 79RC32438 Signal GPIO[30] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIMUINTN Alternate function: PCI Messaging unit interrupt output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[31] SPI Interface SCK I/O I/O Serial Clock. This signal is used as the serial clock output in SPI mode and in PCI satellite mode with suspended CPU execution during PCI serial EEPROM loading. This pin may be configured as a GPIO pin. Serial Data Input. This signal is used to shift in serial data in SPI mode and in PCI satellite mode with suspended CPU execution during PCI serial EEPROM loading. This pin may be configured as a GPIO pin. Serial Data Output. This signal is used shift out serial data in SPI mode and in PCI satellite mode with suspended CPU execution during PCI serial EEPROM loading. This pin may be configured as a GPIO pin. I2C Clock. I2C-bus clock. I2C Data Bus. I2C-bus data bus. SDI I/O SDO I/O I2C Bus Interface SCL SDA Ethernet Interfaces MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER I I I I I I Ethernet 0 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. Ethernet 0 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet 0 MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. Ethernet 0 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. Ethernet 0 MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. Ethernet 0 MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. Ethernet 0 MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet 0 MII Transmit Data. This nibble wide data bus contains the data to be transmitted. Ethernet 0 MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. Ethernet 0 MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters. Ethernet 1 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. Table 1 Pin Description (Part 7 of 9) I/O I/O MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER I O O O MII1CL I 10 of 59 May 25, 2004 IDT 79RC32438 Signal MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER Type I I I I I Name/Description Ethernet 1 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet 1 MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. Ethernet 1 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. Ethernet 1 MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. Ethernet 1 MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. Ethernet 1 MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet 1 MII Transmit Data. This nibble wide data bus contains the data to be transmitted. Ethernet 1 MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. Ethernet 1 MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters. MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management interface. MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY. MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER I O O O MIIMDC MIIMDIO JTAG / EJTAG EJTAG_TMS O I/O I EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller. When using the JTAG boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the system and the processor clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected (since there is an internal pull-up) or driven high. Table 1 Pin Description (Part 8 of 9) JTAG_TCK I JTAG_TDI JTAG_TDO I O JTAG_TMS I 11 of 59 May 25, 2004 IDT 79RC32438 Signal JTAG_TRST_N Type I Name/Description JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high. Debug CPU O CPU Transaction. This signal is asserted during all CPU instruction fetches and data transfers to/from the DDR and devices on the memory and peripheral bus. The signal is negated during PCI and DMA transactions to/from the DDR and devices on the memory and peripheral bus. Instruction or Data. This signal is driven high during CPU instruction fetches on the memory and peripheral bus memory or DDR bus. Table 1 Pin Description (Part 9 of 9) INST O Pin Characteristics Note: Some input pads of the RC32438 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32438's operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Memory and Peripheral Bus Pin Name BDIRN BGN BOEN BRN BWEN[1:0] CSN[5:0] MADDR[21:0] MDATA[15:0] OEN RWN WAITACKN Type O O O I O O O I/O O O I Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL I/O Type High Drive Low Drive High Drive STI2 High Drive High Drive High Drive High Drive High Drive High Drive STI pull-up pull-up Internal Resistor Notes1 Table 2 Pin Characteristics (Part 1 of 4) 12 of 59 May 25, 2004 IDT 79RC32438 Function DDR Bus Pin Name DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN[1:0] DDRCKP[1:0] DDRCSN[1:0] DDRDATA[31:0] DDRDM[7:0] DDRDQS[3:0] DDROEN[3:0] DDRRASN DDRVREF DDRWEN PCI Bus Interface 3 Type O O O O O O O I/O O I/O O O I O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer SSTL_2 SSTL_2 SSTL_2 SSTL_2 / LVCMOS SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 Analog SSTL_2 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL PCI LVTTL PCI LVTTL I/O Type SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Open Collector; PCI PCI PCI Low Drive Internal Resistor Notes1 PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN pull-up on board pull-up on board pull-up on board pull-up on board pull-up on board pull-down on board pull-up on board pull-up on board pull-up on board pull-up pull-up on board General Purpose I/O GPIO[23:0] GPIO[24] GPIO[25] GPIO[30:26] GPIO[31] 4 Low Drive pull-up pull-up on board I/O I/O Low Drive pull-up Table 2 Pin Characteristics (Part 2 of 4) 13 of 59 May 25, 2004 IDT 79RC32438 Function Serial Interface Pin Name SCK SDI SDO I2C-Bus Interface SCL SDA Ethernet Interfaces MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER MIIMDC MIIMDIO EJTAG / ICE JTAG_TRST_N Type I/O I/O I/O I/O I/O I I I I I I I O O O I I I I I I I O O O O I/O I I I O I I O O Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL I/O Type Low Drive Low Drive Low Drive Low Drive/STI Low Drive/STI STI STI STI STI STI STI STI Low Drive Low Drive Low Drive STI STI STI STI STI STI STI Low Drive Low Drive Low Drive Low Drive Low Drive STI STI STI Low Drive STI STI Low Drive Low Drive Internal Resistor pull-up pull-up pull-up Notes1 pull-up on board pull-up on board pull-up on board pull-up on board5 pull-up on board5 pull-down pull-down pull-up pull-up pull-down pull-down pull-up pull-down pull-down pull-up pull-up pull-down pull-down pull-up pull-up pull-up pull-up pull-up JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS EJTAG_TMS Debug CPU INST pull-up pull-up Table 2 Pin Characteristics (Part 3 of 4) 14 of 59 May 25, 2004 IDT 79RC32438 Function Miscellaneous Pin Name CLK EXTCLK COLDRSTN RSTN Type I O I I/O Buffer LVTTL LVTTL LVTTL LVTTL I/O Type STI High Drive STI Low Drive / STI pull-up pull-up on board Internal Resistor Notes1 Table 2 Pin Characteristics (Part 4 of 4) 1. External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table. 2. Schmidt Trigger Input (STI). 3. The PCI pins have internal pull-ups but they are too weak to guarantee system validity. Therefore, board pull-ups are mandatory where indicated. GPIO alternate function pins for PCI must also have board pull-ups. is an alternate function of GPIO[30]. When configured as an alternate function, this pin is tri-stated when not asserted (i.e., it acts as an open collector output). 4. PCIMUINTN 5. Use a 2.2K pull-up resistor for I2C pins. Boot Configuration Vector The boot configuration vector is read by the RC32438 during a cold reset. The vector defines essential RC32438 parameters that are required once the cold reset completes. The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configuration vector read in by the RC32438 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register. Signal MDATA[3:0] Name/Description CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multiplies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For master clock input frequency constraints, refer to Table 3.1 in the RC32438 User Manual. 0x0 - PLL Bypass 0x1 - Multiply by 3 0x2 - Multiply by 4 0x3 - Multiply by 6 0x4 - Multiply by 8 0x5 - reserved 0x6 - reserved 0x7 - reserved 0x8 - reserved 0xD - reserved 0xE - reserved 0xF - reserved External Clock Divider. This field specifies the value by which the IPBus clock (ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock output on the EXTCLK pin. 0x0 - Divide by 1 0x1 - Divide by 2 0x2 - Divide by 4 0x3 - reserved Endian. This bit specifies the endianness. 0x0 - little endian 0x1 - big endian Table 3 Boot Configuration Encoding (Part 1 of 2) MDATA[5:4] MDATA[6] 15 of 59 May 25, 2004 IDT 79RC32438 Signal MDATA[7] Name/Description Boot Device Width. This field specifies the width of the boot device (i.e., Device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles 0x1 - reserved PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial value of the EN bit in the PCIC register is determined by the PCI mode. 0x0 - Disabled (EN initial value is zero) 0x1 - PCI satellite mode with PCI target not ready (EN initial value is one) 0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one) 0x3 - PCI host mode with external arbiter (EN initial value is zero) 0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm (EN initial value is zero) 0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm (EN initial value is zero) 0x6 - reserved 0x7 - reserved Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - Watchdog timer enabled 0x1 - Watchdog timer disabled Reserved. These pins must be driven low during boot configuration. Table 3 Boot Configuration Encoding (Part 2 of 2) MDATA[8] MDATA[11:9] MDATA[12] MDATA[15:13] 16 of 59 May 25, 2004 IDT 79RC32438 Logic Diagram -- RC32438 Miscellaneous Signals CLK COLDRSTN RSTN EXTCLK 2 6 22 16 Ethernet MIIMDC MIIMDIO MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER BDIRN BGN BOEN BRN BWEN[1:0] CSN[5:0] MADDR[21:0] MDATA[15:0] OEN RWN WAITACKN Memory and Peripheral Bus 4 14 2 4 2 2 2 32 4 8 4 4 4 RC32438 DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN[1:0] DDRCKP[1:0] DDRCSN[1:0] DDRDATA[31:0] DDRDM[7:0] DDRDQS[3:0] DDROEN[3:0] DDRRASN DDRVREF DDRWEN DDR Bus EJTAG / JTAG Signals EJTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 32 4 4 Debug Signals INST CPU 4 PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN PCI Bus General Purpose I/O GPIO[31:0] 32 I2C-Bus SDA SCL Serial I/O SDO SDI SCK VccCore VccI/O Vss VccPLL VssPLL Power/Ground Figure 1 Logic Diagram 17 of 59 May 25, 2004 IDT 79RC32438 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. Tlow Tper clock Tdo Output signal 1 Tzd Output signal 2 Tsu Input Signal 1 Tpw Signal 1 Signal 2 Signal 3 Tskew Thld Tdz Tdo Tjitter Trise Tfall Thigh Figure 2 AC Timing Definitions Waveform Symbol Tper Tlow Thigh Trise Tfall Tjitter Tdo Tzd Tdz Tsu Thld Tpw Tslew X(clock) Tskew Clock period. Clock low. Amount of time the clock is low in one clock period. Clock high. Amount of time the clock is high in one clock period. Rise time. Low to high transition time. Fall time. High to low transition time. Definition Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold. The maximum time represents the earliest time the designer can use the data. Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid. Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated. Input set-up. Amount of time before the reference clock edge that the input must be valid. Input hold. Amount of time after the reference clock edge that the input must remain valid. Pulse width. Amount of time the input or output is active for asynchronous signals. Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high. Timing value. This notation represents a value of `X' multiplied by the clock time period of the specified clock. Using 5(CLK) as an example: X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200. Skew. The amount of time two signal edges deviate from one another. Table 4 AC Timing Definitions 18 of 59 May 25, 2004 IDT 79RC32438 System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16. 200MHz Reference Min Max Edge none 200 5.0 none 100 10.0 none 25 15.0 40 -- -- 200 5.0 100 10.0 66.6 40.0 60 3.0 0.1 233MHz Min 200 4.2 100 10.0 25 12.9 40 -- -- Max 233 5.0 116.5 8.5 77.6 40.0 60 3.0 0.1 266MHz Min 200 3.8 100 10.0 25 11.2 40 -- -- Max 266 5.0 133 7.5 88.6 40.0 60 3.0 0.1 300MHz Min 200 3.3 100 6.7 25 10 40 -- -- Max 300 5.0 150 10.0 100 40 60 3.0 0.1 Timing Diagram Reference See Figure 3. Parameter PCLK1 2,3,4 Symbol Frequency Tper Units MHz ns MHz ns MHz ns % of Tper_5a ns ns ICLK Frequency Tper CLK5 Frequency Tper_5a Thigh_5a, Tlow_5a Trise_5a, Tfall_5a Tjitter_5a Table 5 Clock Parameters 1. The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). 2. ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally. 3. The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)). 4. 5. PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66MHz. The input clock (CLK) is input from the external oscillator to the internal PLL. Tper_5a Thigh_5a Tlow_5a CLK Tjitter_5a Tjitter_5a Trise_5a Tfall_5a Figure 3 Clock Parameters Waveform 19 of 59 May 25, 2004 IDT 79RC32438 AC Timing Characteristics Values given below are based on systems running at recommended operating temperatures and supply voltages, shown in Tables 15 and 16. Signal Reset COLDRSTN1 Tpw_6a2 none Trise_6a RSTN3 (input) RSTN (output) MDATA[15:0] (boot vector) 3 Symbol 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference OSC + 0.5 -- 2(CLK) -- 5.0 -- 15.0 -- 30.0 5(CLK) OSC + 0.5 -- 2(CLK) -- 5.0 -- 15.0 -- 30.0 5(CLK) OSC + 0.5 -- 2(CLK) -- 5.0 -- 15.0 -- 30.0 5(CLK) OSC + 0.5 -- 2(CLK) -- 5.0 -- 15.0 -- 30.0 5(CLK) ms ns ns ns ns ns ns ns Cold reset Cold reset Warm reset Cold reset Cold reset Cold reset Warm reset Warm reset See Figures 4 and 5. none Tpw_6b2 none Tdo_6c Thld_6d Tdz_6d2 Tdz_6d2 Tzd_6d2 COLDRSTN falling COLDRSTN rising COLDRSTN falling RSTN falling RSTN rising -- 3.0 -- -- 2(CLK) -- 3.0 -- -- 2(CLK) -- 3.0 -- -- 2(CLK) -- 3.0 -- -- 2(CLK) -- -- -- cc stable. -- Table 6 Reset and System AC Timing Characteristics 1. The COLDRSTN minimum pulse width is the oscillator stabilization time (OSC) plus 0.5 ms with V 2. The values for this symbol were determined by calculation, not by testing. 3. RSTN is a bidirectional signal. It is treated as an asynchronous input. 1 CLK COLDRSTN RSTN MDATA[15:0] BDIRN BOEN EXTCLK Tdz_6d 2 3 4 Trise_6a Thld_6d 5 6 BOOT VECT FFFF_FFFF Tpw_6a 1. 2. 3. 4. 5. 6. <= 16 CLK >= 4096 CLK clock cycles >= 4096 CLK clock cycles clock cycles COLDRSTN asserted by external logic. The RC32438 asserts RSTN, asserts BOEN low, drives BDIRN low, disables EXTCLK, and tri-states the data bus and all output pins in response. External logic begins driving valid boot configuration vector on the data bus, and the RC32438 starts sampling it. External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is negated. The RC32438 stops sampling the boot configuration vector. The RC32438 starts driving the data bus, MDATA[15:0], negates BOEN, drives BDIRN high, and starts driving EXTCLK. RSTN negated by the RC32438. CPU begins executing by taking MIPS reset exception, and the RC32438 starts sampling RSTN as a warm reset input. Figure 4 Cold Reset AC Timing Waveform 20 of 59 May 25, 2004 IDT 79RC32438 1 CLK COLDRSTN RSTN 2 3 4 5 Tdz_6d Tzd_6d MDATA[15:0] Mem Control Signals EXTCLK >= 4096 CLK clock cycles Active Deasserted FFFF_FFFF Active >= 4096 CLK clock cycles (RSTN ignored during this period to allow pull-up to drive signal high) 1. 2. 3. 4. 5. Warm reset caused by any of the conditions listed in the Warm Reset section of Chapter 3, Clocking and Initialization, in the RC32438 User Reference Manual. The RC32438 tri-states the data bus, MDATA[15:0], and negates all memory control signals. The RC32438 negates RSTN. The RC32438 starts driving the data bus, MDATA[15:0], again, but does not sample the RSTN input. CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again. Figure 5 Warm Reset AC Timing Waveform Signal Symbol1 Referenc e Edge 200MHz Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference Memory Bus - DDR Access DDRDATA[31:0] Tskew_7g2 Tdo_7k3 DDRDM[7:0] DDRDQS[3:0] DDRADDR[13:0], DDRBA[1:0], DDRCASN, DDRCKE, DDRCSN[1:0], DDROEN[3:0], DDRRASN, DDRWEN 1. 2. 3. DDRDQSx 0.0 1.5 0.9 3.3 3.3 0.75 4.5 0.0 1.1 1.1 -0.75 1.1 0.9 2.9 2.9 0.75 4.5 0.0 0.9 0.9 -0.75 1.1 0.9 2.7 2.7 0.75 4.5 0.0 0.7 0.7 -0.75 1.1 0.8 2.4 2.4 0.75 4.5 ns ns ns ns ns See Figures 6 and 7. Tdo_7l Tac Tdo_7m4 DDRDQSx DDRCKPx DDRCKPx 1.5 -0.75 1.1 Table 7 DDR SDRAM Timing Characteristics In the DDR data sheet: Tskew_7g = tDQSQ; Tdo_7k = tDH, tDS; Tdo_7l = tDH, tDS; Tac = tAC; Tdo_7m = tIH, tIS. Meets DDR timing requirements for DDR 266 SDRAMs with 400 ps remaining margin to compensate for PCB propagation mismatches, which is adequate to guarantee functional timing, provided the RC32438 DDR layout guidelines are followed. Setup times are calculated as applicable clock period - Tdo max. For example, if the DDR is running at 266MHz, it uses a 133MHz input clock. The period for a 133MHz clock is 7.5ns. If the Tdo max value is 4.5ns, the TIS parameter is 7.5ns minus 4.5ns = 3ns. The DDR spec for this parameter is 1ns, so there is 2ns of slack left over for board propagation. Calculations for TDS are similar, but since this parameter is taken relative to the DDRDQS signals, which are referenced on both edges, the effective period with a 133MHz input clock is only 3.75ns. So, if the max Tdo is 2.7ns, we have 3.75ns minus 2.7ns = 1.05ns for TDS. The DDR data sheet specs a value of 0.5ns for 266MHz, so this leaves 0.55ns slack for board propagation delays. 21 of 59 May 25, 2004 IDT 79RC32438 DDRCKPx DDRCKNx Tdo_7m DDRCSNx Tdo_7m DDRADDR[13:0] DDRCMD1 DDRCKE Tdo_7m DDRBA[1:0] DDRDM[7:0] DDROEN[3:0] DDRDQSx (ideal) DDRDATA[31:0]2 (ideal) Tac (min) DDRDQSx (min) DDRDATA[31:0]2 Tac (max) DDRDQSx (max) DDRDATA[31:0]2 1 RowA Tdo_7m ACTV Col A0 Col A2 RowB NOP NOP RD RD NOP NOP PRECHG NOP ACTV NOP BNKx BNKx BNKx BNKx BNKx D0 D1 D2 D3 Tskew_7g D0 D1 D2 D3 Tskew_7g D0 D1 D2 D3 2 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register (see Chapter 7, DDR Controller, in the RC32438 User Reference Manual). Figure 6 DDR SDRAM AC Timing Waveform - SDRAM Read Access 22 of 59 May 25, 2004 IDT 79RC32438 DDRCKPx DDRCKNx Tdo_7m DDRCSNx Tdo_7m DDRADDR[13:0] DDRCMD1 DDRCKE DDRBA[1:0] DDROEN[3:0] DDRDQSx Tdo_7l DDRDM[7:0] FF DM0 RowA NOP Tdo_7m ACTV NOP Col A0 WR Col A2 WR NOP NOP NOP NOP NOP Tdo_7m BNKx BNKx Tdo_7m Tdo_7l DM1 DM2 DM3 FF DDRDQSx Tdo_7k DDRDATA[31:0]2 1 2 Tdo_7k D1 D2 D3 D0 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register (see Chapter 7, DDR Controller, in the RC32438 User Reference Manual). Figure 7 DDR SDRAM Timing Waveform -- Write Access Signal Symbol 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference See Figures 8 and 9. Memory and Peripheral Bus1 MADDR[21:0] Tdo_8a Tdz_8a2 Tzd_8a2 MADDR[25:22] Tdo_8b Tdz_8b2 Tzd_8b2 EXTCLK rising EXTCLK rising 0.0 0.0 0.5 0.0 0.7 1.2 5.0 0.1 2.3 6.5 1.5 3.3 0.0 0.0 0.5 0.0 0.7 1.2 5.0 0.1 2.3 6.5 1.5 3.3 0.0 0.0 0.5 0.0 0.7 1.2 5.0 0.1 2.3 6.5 1.5 3.3 0.0 0.0 0.5 0.0 0.7 1.2 5.0 0.1 2.3 6.5 1.5 3.3 ns ns ns ns ns ns Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 3) 23 of 59 May 25, 2004 IDT 79RC32438 200MHz Reference Edge Min Max EXTCLK rising 7.0 0.0 0.0 0.0 0.5 none EXTCLK rising 10.0 1.0 -1.0 0.4 EXTCLK rising 1.0 0.1 1.1 EXTCLK rising 5.5 0.0 EXTCLK rising EXTCLK rising 1.0 5.8 0.0 none EXTCLK rising 2(EXTCLK) Signal MDATA[15:0] Symbol Tsu_8c Thld_8c Tdo_8c Tdz_8c 2 233MHz Min 7.0 0.0 0.0 0.0 0.5 8.33 1.0 -1.0 0.4 1.0 0.1 1.1 5.5 0.0 1.0 5.8 0.0 2(EXTCLK) 266MHz Min 7.0 0.0 0.0 0.0 0.5 7.5 1.0 -1.0 0.4 1.0 0.1 1.1 5.5 0.0 1.0 5.8 0.0 2(EXTCLK) 300MHz Min 7.0 0.0 0.0 0.0 0.5 6.66 1.0 -1.0 0.4 1.0 0.1 1.1 5.5 0.0 1.0 5.8 0.0 2(EXTCLK) Max -- -- 4.0 0.1 2.2 -- 4.0 -0.1 1.0 4.0 0.4 2.0 -- -- 4.0 -- -- -- 4.0 0.4 2.2 4.0 0.1 1.1 4.0 0.2 1.5 4.0 0.2 1.7 Max -- -- 4.0 0.1 2.2 -- 4.0 -0.1 1.0 4.0 0.4 2.0 -- -- 4.0 -- -- -- 4.0 0.4 2.2 4.0 0.1 1.1 4.0 0.2 1.5 4.0 0.2 1.7 Max -- -- 4.0 0.1 2.2 -- 4.0 -0.1 1.0 4.0 0.4 2.0 -- -- 4.0 -- -- -- 4.0 0.4 2.2 4.0 0.1 1.1 4.0 0.2 1.5 4.0 0.2 1.7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Timing Diagram Reference See Figures 8 and 9 (cont.) -- -- 4.0 0.1 2.2 -- 4.0 -0.1 1.0 4.0 0.4 2.0 -- -- 4.0 -- -- -- 4.0 0.4 2.2 4.0 0.1 1.1 4.0 0.2 1.5 4.0 0.2 1.7 Tzd_8c2 EXTCLK BDIRN 3 Tper_8d Tdo_8e Tdz_8e 2 Tzd_8e2 BOEN Tdo_8f Tdz_8f2 Tzd_8f BRN 2 Tsu_8g Thld_8g BGN WAITACKN 4 Tdo_8h Tsu_8h Thld_8h Tpw_8h2 CSN[5:0] Tdo_8i Tdz_8i2 Tzd_8i 2 0.0 0.1 0.6 0.0 0.1 0.6 0.0 -0.7 0.6 0.0 -0.4 0.8 0.0 0 0.8 0.0 0.1 0.6 0.0 -0.7 0.6 0.0 -0.4 0.8 0.0 0 0.8 0.0 0.1 0.6 0.0 -0.7 0.6 0.0 -0.4 0.8 0.0 0 0.8 RWN Tdo_8j Tdz_8j2 Tzd_8j 2 EXTCLK rising 0.0 -0.7 0.6 OEN Tdo_8k Tdz_8k2 Tzd_8k2 EXTCLK rising 0.0 -0.4 0.8 BWEN[1:0] Tdo_8l Tdz_8l2 Tzd_8l 2 EXTCLK rising 0.0 0 0.8 Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 2 of 3) 24 of 59 May 25, 2004 IDT 79RC32438 200MHz Reference Edge Min Max None EXTCLK rising 2(ICLK) Signal DMAREQN[1:0] DMADONEN[1:0] Symbol Tpw_8n2 Tsu_8o Thld_8o 233MHz Min 2(ICLK) 266MHz Min 2(ICLK) 300MHz Min 2(ICLK) Max Max -- -- -- 6.0 10.0 Max -- -- -- 6.0 10.0 Unit ns ns ns ns ns Conditions Timing Diagram Reference See Figures 10 and 11. -- -- -- 6.0 10.0 6.0 1.0 6.0 1.0 1.5 2.0 -- -- 6.0 10.0 6.0 1.0 1.5 2.0 6.0 1.0 1.5 2.0 DMAFINN[1:0] CPU, INST Tdo_8p Tdo_8m EXTCLK rising EXTCLK rising 1.5 2.0 See Figures 8 and 9. Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 3 of 3) 1. The RC32438 provides bus turnaround cycles to prevent bus contention when going from 2. a read to write, write to read, and during external bus ownership. For example, there are no cycles where an external device and the RC32438 are both driving. See Chapter 6, Device Controller, in the RC32438 User Reference Manual. The values for this symbol were determined by calculation, not by testing. 3. The frequency of EXTCLK is programmable. See the External Clock Divider description in Table 3 of this data sheet. 4. WAITACKN must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. Tper_8d EXTCLK Tdo_8a MADDR[21:0] Tdo_8b MADDR[25:22] RWN Tdo_8i Addr[25:22] Addr[21:0] Thigh_8d Tlow_8d Tdo_8i CSN[5:0] BWEN[1:0] Tdo_8k OEN 1111 Tdo_8k Thld_8c Tdz_8c MDATA[15:0] Tdo_8e BDIRN Tdo_8f BOEN WAITACKN Tdo_8m CPU, INST RC32438 samples read data Tsu_8c Data Tzd_8c Tdo_8e Tdo_8f Tdo_8m Figure 8 Memory and Peripheral Bus AC Timing Waveform -- Read Access 25 of 59 May 25, 2004 IDT 79RC32438 EXTCLK Tdo_8a MADDR[21:0] Tdo_8b MADDR[25:22] Tdo_8j RWN Tdo_8i Addr[25:22] Addr[21:0] CSN[5:0] Tdo_8l BWEN[1:0] OEN Tdo_8c MDATA[15:0] BDIRN Tdo_8f 1111 Byte Enables 1111 Data BOEN WAITACKN CPU, INST Tdo_8m Figure 9 Memory and Peripheral Bus AC Timing Waveform -- Write Access EXTCLK Tsu_8o DMADONENx MDATA[15:0] MADDR[25:0] Tdo_8p DMAFINNx Figure 10 DMADONEN and DMAFINN AC Timing Waveform data address Thld_8o Tdo_8p 26 of 59 May 25, 2004 IDT 79RC32438 EXTCLK DMAREQN Tpw_8n ICLK CSN Tpw_8n Tpw_8n is the minimum amount of time before DMAREQN is recognized as asserted or deasserted. Figure 11 DMAREQN AC Timing Waveform Signal Ethernet1 MIIMDC Symbol 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference Tper_9a Thigh_9a, Tlow_9a None 40.0 16.0 -- -- -- -- 300 33.3 13.0 10.0 0.0 10 -- -- -- -- 300 30.0 12.0 10.0 0.0 10 -- -- -- -- 300 30.0 12.0 10.0 0.0 10 -- -- -- -- 300 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 Mbps 10 Mbps See Figure 12. MIIMDIO Tsu_9b Thld_9b Tdo_9b 2 MIIMDC rising 10.0 0.0 10 MIIxRXCLK, MIIxTXCLK3 Tper_9c Thigh_9c, Tlow_9c Trise_9c, Tfall_9c None 399.96 400.4 399.96 400.4 399.96 400.4 399.96 400.4 140 -- 260 3.0 40.0 26.0 2.0 -- -- 25.0 140 -- 39.9 14.0 -- 10.0 10.0 0.0 260 3.0 40.0 26.0 2.0 -- -- 25.0 140 -- 39.9 14.0 -- 10.0 10.0 0.0 260 3.0 40.0 26.0 2.0 -- -- 25.0 140 -- 39.9 14.0 -- 10.0 10.0 0.0 260 3.0 40.0 26.0 2.0 -- -- 25.0 MIIxRXCLK, MIIxTXCLK3 Tper_9d Thigh_9d, Tlow_9d Trise_9d, Tfall_9d None 39.9 14.0 -- MIIxRXD[3:0], MIIxRXDV, MIIxRXER MIIxTXD[3:0], MIIxTXENP, MIIxTXER Tsu_9e Thld_9e Tdo_9f MIIxRXCLK rising MIIxTXCLK rising 10.0 10.0 0.0 Table 9 Ethernet AC Timing Characteristics 1. There are two MII interfaces and the timing is the same for each. "X" represents interface 0 or 1. 2. The values for this symbol were determined by calculation, not by testing. 27 of 59 May 25, 2004 IDT 79RC32438 3. The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)). Thigh_9d Tper_9d MIIxRXCLK Thld_9e Tsu_9e MIIxRXDV, MIIxRXD[3:0], MIIxRXER Thigh_9d Tper_9d MIIxTXCLK Tdo_9f Tdo_9f MIIxTXEN, MIIxTXD[3:0], MIIxTXER Thigh_9a Tper_9a MIIxMDC Tdo_9b MIIxMDIO (output) Tlow Tlow_9d Tlow Tlow_9d Tlow_9a Tlow Tdo_9b Thld_9b Tsu_9b MIIxMDIO (input) Figure 12 Ethernet AC Timing Waveform 28 of 59 May 25, 2004 IDT 79RC32438 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Timing Diagram Reference Signal PCI1 PCICLK2 Symbol Unit Conditions Tper_10a Thigh_10a, Tlow_10a Tslew_10a none 15.0 6.0 1.5 30.0 -- 4.0 -- -- 6.0 14.0 -- -- -- 6.0 -- -- -- -- -- 6.0 11.1 15.0 6.0 1.5 3.0 0 2.0 -- 2.0 5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7 30.0 -- 4.0 -- -- 6.0 14.0 -- -- -- 6.0 -- -- -- -- -- 6.0 11.1 15.0 6.0 1.5 3.0 0 2.0 -- 2.0 5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7 30.0 -- 4.0 -- -- 6.0 14.0 -- -- -- 6.0 -- -- -- -- -- 6.0 11.1 15.0 6.0 1.5 3.0 0 2.0 -- 2.0 5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7 30.0 -- 4.0 -- -- 6.0 14.0 -- -- -- 6.0 -- -- -- -- -- 6.0 11.1 ns ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 66 MHz PCI See Figure 13. PCIAD[31:0], PCIBEN[3:0], PCIDEVSELN, PCIFRAMEN,PCIIRDYN, PCILOCKN, PCIPAR, PCIPERRN, PCISTOPN, PCITRDY PCIGNTN[3:0], PCIREQN[3:0] Tsu_10b Thld_10b Tdo_10b Tdz_10b3 Tzd_10b 3 PCICLK rising 3.0 0 2.0 -- 2.0 See Figure 13 (cont.) Tsu_10c Thld_10c Tdo_10c 4 PCICLK rising 5.0 0 2.0 PCIRSTN (output) Tpw_10d3 None 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 See Figures 15 and 16 PCIRSTN (input)4,5 Tpw_10e3 None Tdz_10e3 PCIRSTN falling PCICLK rising PCISERRN6 Tsu_10f Thld_10f Tdo_10f See Figure 13 PCIMUINTN 1. 6 Tdo_10g PCICLK rising 4.7 Table 10 PCI AC Timing Characteristics This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2. The values for this symbol were determined by calculation, not by testing. PCIRSTN is an output in host mode and an input in satellite mode. PCISERRN and PCIMUINTN use open collector I/O types. 2. PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66MHz. 3. 4. 5. To meet the PCI delay specification from reset asserted to outputs floating, the PCI reset should be logically combined with the COLDRSTN input, instead of input on PCIRSTN. 6. 29 of 59 May 25, 2004 IDT 79RC32438 Thigh_10a Tper_10a PCICLK Tdo_10b Bussed output Tdo_10c Point to point output Thld_10b Tsu_10b Bussed input Tsu_10c Point to point input valid valid Tlow_10a Tdz_10b Tzd_10b Thld_10c Figure 13 PCI AC Timing Waveform COLDRSTN cold reset PCIRSTN (output) RSTN (tri-state) Tpw_10d PCI interface enabled warm reset Note: During and after cold reset, PCIRSTN is tri-stated and requires a pull-down to reach a low state. After the PCI interface is enabled in host mode, PCIRSTN will be driven either high or low depending on the reset state of the 79RC32438. Figure 14 PCI AC Timing Waveform -- PCI Reset in Host Mode CLKP Tpw_10e PCIRSTN (input) RSTN Tdz_10e MDATA[15:0] PCI bus signals Figure 15 PCI AC Timing Waveform -- PCI Reset in Satellite Mode warm reset 30 of 59 May 25, 2004 IDT 79RC32438 Signal I2C1 SCL Symbol 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference Frequency Thigh_12a, Tlow_12a Trise_12a Tfall_12a none 0 4.0 -- -- 100 -- 1000 300 -- 3.45 1000 300 -- -- -- -- 0 4.0 -- -- 250 0 -- -- 4.7 4.0 4.0 4.7 100 -- 1000 300 -- 3.45 1000 300 -- -- -- -- 0 4.0 -- -- 250 0 -- -- 4.7 4.0 4.0 4.7 100 -- 1000 300 -- 3.45 1000 300 -- -- -- -- 0 4.0 -- -- 250 0 -- -- 4.7 4.0 4.0 4.7 100 -- 1000 300 -- 3.45 1000 300 -- -- -- -- kHz s ns ns ns s ns ns s s s s 100 KHz See Figure 16. SDA Tsu_12b Thld_12b Trise_12b Tfall_12b SCL rising 250 0 -- -- Start or repeated start condition Stop condition Bus free time between a stop and start condition SCL Tsu_12c Thld_12c Tsu_12d Tdelay_12e SDA falling SDA rising 4.7 4.0 4.0 4.7 Frequency Thigh_12a, Tlow_12a Trise_12a Tfall_12a none 0 0.6 -- -- 400 -- 300 300 -- 0.9 300 300 -- -- -- -- 0 0.6 -- -- 100 0 -- -- 0.6 0.6 0.6 1.3 400 -- 300 300 -- 0.9 300 300 -- -- -- -- 0 0.6 -- -- 100 0 -- -- 0.6 0.6 0.6 1.3 400 -- 300 300 -- 0.9 300 300 -- -- -- -- 0 0.6 -- -- 100 0 -- -- 0.6 0.6 0.6 1.3 400 -- 300 300 -- 0.9 300 300 -- -- -- -- kHz s ns ns ns s ns ns s s s s 400 KHz SDA Tsu_12b Thld_12b Trise_12b Tfall_12ba SCL rising 100 0 -- -- Start or repeated start condition Stop condition Bus free time between a stop and start condition 1. Tsu_12c Thld_12c Tsu_12d Tdelay_12e SDA falling SDA rising 0.6 0.6 0.6 1.3 Table 11 I2C AC Timing Characteristics For more information, see the I C-Bus specification by Philips Semiconductor. 2 31 of 59 May 25, 2004 IDT 79RC32438 Tdelay_12e SDA Tlow_12a Thld_12c Thigh_12a Thld_12b Tsu_12b Tsu_12c Thld_12c Tsu_12d SCL Figure 16 I2C AC Timing Waveform Signal GPIO GPIO[31:0]1 Symbol 200MHz 233MHz 266MHz 300MHz Reference Edge Min Max Min Max Min Max Min Max Unit Conditions Timing Diagram Reference Tpw_13b2 None 2(ICLK) -- 2(ICLK) -- 2(ICLK) -- 2(ICLK) -- ns See Figure 17. Table 12 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK Tdo_13a GPIO (synchronous output) Thld_13a Tsu_13a GPIO (synchronous input) Tpw_13b GPIO (asynchronous input) Figure 17 GPIO AC Timing Waveform Tdo_13a 32 of 59 May 25, 2004 IDT 79RC32438 200MHz 233MHz 266MHz 300MHz Reference Edge Min Max Min Max Min Max Min Max Timing Diagram Reference Signal SPI1 SCK Symbol Unit Conditions Tper_15a Tper_15a Tper_15a Thigh_15a, Tlow_15a Thigh_15a, Tlow_15a Thigh_15a, Tlow_15a None -- -- 1920 960 -- -- 1920 960 -- -- 1920 960 -- -- 1920 960 ns ns ns ns ns ns ns ns ns ns ns 33 MHz PCI 66 MHz PCI SPI 33 MHz PCI 66 MHz PCI SPI SPI or PCI See Figures 18, 19, 20 and 21. 100 166667 100 166667 100 166667 100 166667 930 465 40 SCK rising or falling SCK rising or falling SCK rising or falling None 60 60 0 0 2(ICLK) 990 495 83353 -- -- 60 60 -- 930 465 40 60 60 0 0 2(ICLK) 990 495 83353 -- -- 60 60 -- 930 465 40 60 60 0 0 2(ICLK) 990 495 83353 -- -- 60 60 -- 930 465 40 60 60 0 0 2(ICLK) 990 495 83353 -- -- 60 60 -- SDI Tsu_15b Thld_15b SDO PCIEECS2 SCK, SDI, SDO3 Tdo_15c Tdo_15d Tpw_15e SPI or PCI PCI Bit I/O Table 13 SPI AC Timing Characteristics 1. In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising. 2. PCIEECS is the PCI serial EEPROM chip select. It is an alternate function of PCIGNTN[1]. 3. In Bit I/O mode, SCK, SDI, and SDO must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tper_15a SCK Tdo_15d PCIEECS Thigh_15a Tlow_15a Tsu_15b SDI MSB bit 6 bit 5 bit 4 bit 3 Thld_15b bit 2 bit 1 LSB Tdo_15c SDO MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Loading PCI configuration registers through SPI from an EEPROM. Figure 18 SPI AC Timing Waveform -- PCI Configurations Load 33 of 59 May 25, 2004 IDT 79RC32438 Thigh_15a Tper_15a SCK Tlow_15a Thld_15b Tsu_15b SDI MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Tdo_15c SDO MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Control bits CPOL = 0, CPHA = 0 in the SPI Control Register, SPC. Figure 19 SPI AC Timing Waveform -- Clock Polarity 0, Clock Phase 0 Thigh_15a Tper_15a SCK Tsu_15b SDI MSB bit 6 bit 5 bit 4 Tlow_15a Thld_15b bit 3 bit 2 bit 1 LSB Tdo_15c SDO MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Control bits CPOL = 0, CPHA = 1 in the SPI Control Register, SPC. Figure 20 SPI AC Timing Waveform -- Clock Polarity 0, Clock Phase 1 EXTCLK Tdo_15e SCK, SDI, SDO (output) Thld_15e Tsu_15e SCK, SDI, SDO (input) Tpw_15e SCK, SDI, SDO (asynchronous input) Tdo_15e Figure 21 SPI AC Timing Waveform -- Bit I/O Mode 34 of 59 May 25, 2004 IDT 79RC32438 Signal EJTAG and JTAG JTAG_TCK Symbol 200MHz Reference Edge Min Max 233MHz Min Max 266MHz Min Max 300MHz Min Max Unit Conditions Timing Diagram Reference Tper_16a Thigh_16a, Tlow_16a none 25.0 10.0 50.0 25.0 -- -- 11.3 11.3 -- -- -- 2 25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0 -- 50.0 25.0 -- -- 11.3 11.3 -- -- -- 2 25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0 -- 50.0 25.0 -- -- 11.3 11.3 -- -- -- 2 25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0 -- 50.0 25.0 -- -- 11.3 11.3 -- -- -- 2 ns ns ns ns ns ns ns ns ns sec See Figure 22. JTAG_TMS1, JTAG_TDI JTAG_TDO Tsu_16b Thld_16b Tdo_16c Tdz_16c2 2 JTAG_TCK rising JTAG_TCK falling none JTAG_TCK rising none 2.4 1.0 -- -- 25.0 2.0 1.0 -- JTAG_TRST_N EJTAG_TMS 1 Tpw_16d Tsu_16e Thld_6e VSENSE Trise_16f Measured from See Figure 24. 0.5V (Tactive) Table 14 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when either JTAG_TMS or EJTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. 2. The values for this symbol were determined by calculation, not by testing. 35 of 59 May 25, 2004 IDT 79RC32438 Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Thld_16e Tsu_16e EJTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 22 JTAG AC Timing Waveform Tdz_16c Tper_16a The IEEE 1149.1 specification requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for a boundary scan or a probe. Reset can occur through a pull-down resistor on JTAG_TRST_N if the probe is not connected. However, on-chip pull-up resistors are implemented on the RC32438 due to an IEEE 1149.1 requirement. Having on-chip pull-up and external pull-down resistors for the JTAG_TRST_N signal requires special care in the design to ensure that a valid logical level is provided to JTAG_TRST_N, such as using a small external pull-down resistor to ensure this level overrides the on-chip pull-up. An alternative is to use an active power-up reset circuit for JTAG_TRST_N, which drives JTAG_TRST_N low only at power-up and then holds JTAG_TRST_N high afterwards with a pull-up resistor. Figure 23 shows the electrical connection of the EJTAG probe target system connector. VDD Pull-up RC32438 JTAG_TRST_N JTAG_TDI JTAG_TDO EJTAG_TMS JTAG_TCK Pull-up TRST* TDI Series-res. 1 GND GND GND GND GND VSENSE GND TDO TMS TCK RST* DINT no connect Pull-down COLDRSTN or RSTN Other reset sources VccIO voltage reference Target System Reset Circuit GND Figure 23 Target System Electrical EJTAG Connection 36 of 59 May 25, 2004 IDT 79RC32438 Using the EJTAG Probe In Figure 23, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k because a low value reduces crosstalk on the cable to the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33 . Recommended resistor values have 5% tolerance. If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The pull-up resistor value of around 47 k should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the signals of the chip with EJTAG. If a probe is used, the RST* signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a voltage reference that drops rapidly to below 0.5V when the target system loses power, even with a capacitive load of 25pF. The probe can thus detect the lost power condition. For additional information on EJTAG, refer to Chapter 20 of the RC32438 User Reference Manual. Voltage Sense Signal Timing Trise_16f VSENSE Tactive Figure 24 Voltage Sense Signal Timing The target system must ensure that Trise is obeyed after the system reaches 0.5V (Tactive), so the probe can use this value to determine when the target has powered-up. The probe is allowed to measure the Trise time from a higher value than Tactive (but lower than Vcc I/O minimum) because the stable indication in this case comes later than the time when target power is guaranteed to be stable. If JTAG_TRST_N is asserted by a pulse at power-up, this reset must be completed after Trise. If JTAG_TRST_N is asserted by a pull-down resistor, the probe will control JTAG_TRST_N. At power-down, no power is indicated to the probe when Vcc I/O drops under the Tactive value, which the probe uses to stop driving the input signals, except for the probe RST*. Phase-Locked Loop (PLL) The phase-locked loop (PLL) multiplies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limited range. PLL Filters It is recommended that the system designer provide a filter network of passive components for the PLL analog and digital power supplies. The PLL circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 25. Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application. 37 of 59 May 25, 2004 IDT 79RC32438 10 ohm1 Vcc 10 F Vss 0.1 F 100 pF RC32438 VccPLL VccPLL VssPLL VssPLL Figure 25 PLL Filter Circuit for Noisy Environments Recommended Operating Supply Voltages Symbol Vss VssPLL VccI/O VccSI/O VccPLL VccCore DDRVREF2 VTT3 Parameter Common ground PLL ground I/O supply except for SSTL_21 I/O supply for SSTL_21 PLL supply 200MHz, 233MHz 266MHz, 300MHz Internal logic supply 200MHz, 233MHz 266MHz, 300MHz SSTL_2 input reference voltage SSTL_2 termination voltage All speeds 3.0 2.3 1.1 1.2 1.1 1.2 0.5(VccSI/O) DDRVREF - 0.04 Table 15 RC32438 Operating Voltages 1. SSTL_2 I/Os are used to connect to DDR SDRAM. 2. Peak-to-peak AC noise on DDRVREF may not exceed 2% DDRVREF (DC). 3. Clock Speed All speeds Minimum 0 Typical 0 Maximum 0 Unit V 3.3 2.5 1.2 1.3 1.2 1.3 0.5(VccSI/O) DDRVREF 3.6 2.7 1.3 1.4 1.3 1.4 0.5(VccSI/O) DDRVREF + 0.04 V V V V V V V V VTT of the SSTL_2 transmitting device must track DDRVREF of the receiving device. Recommended Operating Temperatures Grade Commercial Industrial Temperature 0C to +70C Ambient -40C to +85C Ambient Table 16 RC32438 Operating Temperatures Capacitive Load Deration Refer to the 79RC32438 IBIS Model on the IDT web site (www.idt.com). 38 of 59 May 25, 2004 IDT 79RC32438 Power-on Sequence Three power-on sequences are given below. Sequence #1 is recommended because it will prevent I/O conflicts and will also allow the input signals to propagate when the I/O powers are brought up. Note: The ESD diodes may be damaged if one of the voltages is applied and one of the other voltages is at a ground level. A. Recommended Sequence t2 > 0 whenever possible (VccCore) t1 - t2 can be 0 (VccSI/O followed by VccI/O) VccI/O 3.3V VccSI/O 2.5V VccCore 1.2V VccI/O -- 3.3V VccSI/O -- 2.5V VccCore (266/300MHz) -- 1.3V VccCore (200/233MHz) -- 1.2V t2 t1 Time B. Reverse Voltage Sequence If sequence A is not feasible, then Sequence B can be used: t1 <50ms and t2 <50ms to prevent damage. Vcc3.3 VccI/O Vcc2.5 VccSI/O VccCore Vcc1.2 VccI/O -- 3.3V VccSI/O -- 2.5V VccCore (266/300MHz) -- 1.3V VccCore (200/233MHz) -- 1.2V t1 t2 Time C. Simultaneous Power-up VccI/O, VccSI/O, and VccCore can be powered up simultaneously. 39 of 59 May 25, 2004 IDT 79RC32438 Power Consumption Parameter 200MHz Typ. Icc I/O Icc SI/O Icc Core, Icc PLL Power Dissipation Normal mode Normal mode 130 100 460 Max. 150 120 500 233MHz Typ. 180 150 510 Max. 200 170 550 266MHz Typ. 220 200 610 Max. 250 220 650 300MHz Typ. 260 250 680 Max. 300 270 730 mA mA mA Unit Conditions CL = 35 pF Tambient = 25oC Max. values use the maximum voltages listed in Table 15. Typical values use the typical voltages listed in that table. 1.2 1.6 1.6 1.9 2.0 2.4 2.4 2.7 W Table 17 RC32438 Power Consumption DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 15. Note: See Table 2, Pin Characteristics, for a complete I/O listing. I/O Type LOW Drive Output HIGH Drive Output Schmitt Trigger Input (STI) SSTL_2 (for DDR SDRAM) Parameter IOL IOH IOL IOH VIL VIH IOL IOH VIL VIH Min. -- -- -- -- -0.3 2.0 7.6 -7.6 -0.3 0.5(VccSI/O) + 0.18 Typical 14.0 -12.0 24.0 -42.0 -- -- Max. -- -- -- -- 0.8 VccI/O + 0.5 Unit mA mA mA mA V V mA mA V V Conditions VOL = 0.4V VOH = 1.5V VOL = 0.4V VOH = 1.5V -- -- VOL = 0.5V VOH = 1.76V -- -- -- -- -- -- 0.5(VccSI/O) - 0.18 VccSI/O + 0.3 Table 18 DC Electrical Characteristics (Part 1 of 2) 40 of 59 May 25, 2004 IDT 79RC32438 I/O Type PCI Parameter IOH(AC) Switching Min. -12(VccI/O) -17.1(VccI/O - VOUT) Typical Max. -- -- -32(VccI/O) Unit mA mA -- mA mA +38(VccI/O) 0.3(VccI/O) 5.5 8.0 + 10 + 10 + 80 mA V V pF -- Vcc (max) Vcc (max) Vcc (max) Conditions 0 < VOUT < 0.3(VccI/O) 0.3(VccI/O) < VOUT < 0.9(VccI/O) 0.7(VccI/O) VccI/O > VOUT > 0.6(VccI/O) 0.6(VccI/O) > VOUT > 0.1(VccI/O) VOUT = 0.18(VccI/O) -- -- -- -- -- -- -- -- -- -- -- -- -- IOL(AC) Switching +16(VccI/O) +26.7(VOUT) -- VIL VIH Capacitance Leakage CIN -0.3 0.5(VccI/O) -- -- -- -- Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK with Pull-ups/downs A A A Table 18 DC Electrical Characteristics (Part 2 of 2) AC Test Conditions Input Reference Voltage 50 RC32438 Output . 50 Test Point Value Parameter Input pulse levels Input rise/fall Input reference level Output reference levels AC test load SSTL I/O 0 to 2.5 0.8 0.5(VccSI/O) 1.25 35 Other I/O 0 to 3.3 1.0 0.5(VccI/O) 1.5 35 Units V ns V V pF Figure 26 AC Test Conditions 41 of 59 May 25, 2004 IDT 79RC32438 Absolute Maximum Ratings Symbol VCCI/O VCCSI/O VCCCore VCCPLL VinI/O VinSI/O Ta Industrial Ta Commercial Ts 1. Parameter I/O supply except for SSTL_22 I/O supply for SSTL_2 Core Supply Voltage PLL supply I/O Input Voltage except for SSTL_2 I/O Input Voltage for SSTL_2 Ambient Operating Temperature Ambient Operating Temperature Storage Temperature 2 Min1 -0.6 -0.6 -0.6 -0.6 -0.6 -0.6 -40 0 -40 Max1 4.0 3.0 2.0 2.0 VccI/O+ 0.5 VccSI/O+ 0.5 +85 +70 +125 Unit V V V V V V C C C Table 19 Absolute Maximum Ratings Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. SSTL_2 I/Os are used to connect to DDR SDRAM. 42 of 59 May 25, 2004 IDT 79RC32438 Package Pin-out -- 416-PBGA Signal Pinout for RC32438 The following table lists the pin numbers, signal names, and number of alternate functions for the RC32438 device. Signal names ending with an "_N" or "N" are active when low. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 Function MII0CL GPIO[25] GPIO[31] CSN[05] CSN[02] BWEN[01] BOEN MDATA[15] MDATA[14] MDATA[10] MDATA[07] MDATA[06] GPIO[29] GPIO[22] MADDR[21] MADDR[19] MADDR[16] MADDR[13] MADDR[10] MADDR[07] MADDR[05] MADDR[02] RSTN DDRDATA[02] DDRDATA[04] DDRDATA[05] MII0CRS WAITACKN RWN CSN[04] CSN[01] BWEN[00] BGN MDATA[13] 1 1 Alt Pin D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 Vss Vss Vcc Core Vcc Core Vcc Core Vss Vss Vss Vss Vcc I/O Vcc SI/O Vcc SI/O Vcc SI/O Vcc SI/O DDRDATA[11] DDRDATA[10] MII0TXD[02] MII0TXD[00] MII0TXD[01] Vss Vcc SI/O DDRDATA[09] DDRDATA[12] DDRDM[01] MII0TXER MII0TXD[03] MII0TXENP Vss Vcc SI/O DDRDQS[01] DDRDATA[15] DDRDATA[14] MII0RXER MII0RXDV Function Alt Pin P1 P2 P3 P4 P23 P24 P25 P26 R1 R2 R3 R4 R23 R24 R25 R26 T1 T2 T3 T4 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 Function GPIO[00] MIIMDIO GPIO[02] Vcc I/O Vcc CORE DDRDM[03] DDRDATA[31] DDRDATA[30] INST EJTAG_TMS Vss Vcc I/O Vcc SI/O DDRDATA[29] DDRADDR[13] DDRCSN[01] NC GPIO[03] CPU Vcc I/O Vcc SI/O DDRCSN[00] DDRADDR[10] DDRADDR[12] JTAG_TDI JTAG_TCK JTAG_TDO Vcc I/O Vss DDRADDR[11] DDRWEN DDRADDR[09] SDO SDI 1 1 Alt 1 Pin AC17 Vss AC18 Vss AC19 Vss AC20 Vcc I/O AC21 Vcc I/O AC22 Vcc I/O AC23 Vcc SI/O AC24 Vcc SI/O AC25 DDROEN[00] AC26 DDRADDR[00] AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 JTAG_TRST_N JTAG_TMS GPIO[15] SDA GPIO[27] PCIAD[30] PCIAD[26] PCICBEN[03] PCIAD[21] 1 1 Function Alt AD10 PCIAD[18] AD11 PCIREQN[01] AD12 PCICLK AD13 PCIGNTN[00] AD14 PCIIRDYN AD15 PCISTOPN AD16 PCIPERRN AD17 PCIAD[15] AD18 PCIAD[11] AD19 PCIAD[08] AD20 PCIAD[06] AD21 PCIGNTN[03] AD22 PCIAD[00] AD23 PCIAD[04] AD24 DDRDM[05] Table 20 RC32438 416-pin Signal Pin-Out (Part 1 of 3) 43 of 59 May 25, 2004 IDT 79RC32438 Pin B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Function MDATA[11] MDATA[03] MDATA[08] MDATA[02] GPIO[23] MADDR[20] GPIO[20] MADDR[17] MADDR[14] MADDR[12] MADDR[09] MADDR[06] MADDR[03] MADDR[00] DDRDATA[01] DDRDQS[00] DDRDM[00] DDRDATA[06] MII0RXD[00] MII0RXCLK EXTCLK COLDRSTN OEN CSN[03] CSN[00] BRN BDIRN MDATA[12] MDATA[09] MDATA[01] MDATA[05] MDATA[04] MDATA[00] GPIO[21] MADDR[18] MADDR[15] MADDR[11] 1 1 1 Alt Pin G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L23 L24 L25 Function MII0TXCLK Vss Vss DDRCKP[00] DDRDATA[16] DDRDATA[13] MII1CRS MII1CL MII1RXCLK Vss Vss DDRCKN[00] DDRDATA[18] DDRVREF MII1RXD[01] MII1RXD[00] MII1RXD[03] Vss Vss DDRDATA[17] DDRDATA[21] DDRDATA[19] MII1RXDV MII1RXD[02] MII1TXCLK Vcc Core Vss DDRDATA[20] DDRDQS[02] DDRCKE MII1TXD[00] MII1RXER MII1TXD[03] Vcc Core Vcc Core DDRDM[02] DDRDATA[24] Alt Pin V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 Function GPIO[05] Vss Vss DDRADDR[08] DDRRASN DDRCASN GPIO[04] SCK CLK Vss Vss DDRADDR[07] DDRADDR[06] DDRBA[01] GPIO[06] Vcc PLL GPIO[08] Vss Vss DDRCKN[01] DDRBA[00] DDRADDR[05] Vss PLL GPIO[07] Vcc PLL Vss Vss DDRCKP[01] DDRADDR[03] DDRADDR[04] GPIO[09] GPIO[14] GPIO[11] Vss Vss Vcc SI/O DDRADDR[01] 1 1 1 1 1 1 1 Alt 1 Pin Function Alt AD25 DDROEN[02] AD26 DDROEN[01] AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 N/C GPIO[13] GPIO[18] GPIO[24] GPIO[26] PCIAD[31] PCIAD[28] PCIAD[25] GPIO[30] 1 1 1 1 1 AE10 PCIAD[22] AE11 PCIAD[19] AE12 PCIAD[16] AE13 PCIRSTN AE14 PCIREQN[02] AE15 PCIFRAMEN AE16 PCIDEVSELN AE17 PCILOCKN AE18 PCICBEN[01] AE19 PCIAD[13] AE20 PCIAD[10] AE21 PCICBEN[00] AE22 PCIAD[05] AE23 PCIAD[02] AE24 PCIGNTN[01] AE25 DDRDM[07] AE26 DDRDM[04] AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 GPIO[16] GPIO[17] GPIO[19] SCL GPIO[28] PCIAD[29] PCIAD[27] PCIAD[24] PCIAD[23] 1 1 1 1 Table 20 RC32438 416-pin Signal Pin-Out (Part 2 of 3) 44 of 59 May 25, 2004 IDT 79RC32438 Pin C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Function MADDR[08] MADDR[04] MADDR[01] DDRDATA[00] DDRDATA[03] DDRDATA[08] DDRDATA[07] MII0RXD[03] MII0RXD[01] MII0RXD[02] Vss Vss Vss Vcc I/O Vcc I/O Vcc I/O Vss Alt Pin L26 M1 M2 M3 M4 M23 M24 M25 M26 N1 N2 N3 N4 N23 N24 N25 N26 Function DDRDATA[22] MII1TXD[02] MII1TXD[01] MIIMDC Vcc Core Vcc Core DDRDATA[23] DDRDATA[27] DDRDATA[25] MII1TXER MII1TXENP GPIO[01] Vcc Core Vcc Core DDRDATA[26] DDRDATA[28] DDRDQS[03] 1 Alt Pin AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 Function DDRADDR[02] Vss PLL GPIO[10] GPIO[12] Vss Vss Vss Vcc I/O Vcc I/O Vcc I/O Vss Vss Vss Vcc Core Vcc Core Vcc Core Vss 1 1 Alt Pin AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function PCIAD[20] PCIAD[17] PCIREQN[03] PCIREQN[00] PCICBEN[02] PCITRDYN PCISERRN PCIPAR PCIAD[14] PCIAD[12] PCIAD[09] PCIAD[07] PCIAD[03] PCIAD[01] PCIGNTN[02] DDRDM[06] DDROEN[03] Alt Table 20 RC32438 416-pin Signal Pin-Out (Part 3 of 3) RC32438 Power Pins Vcc I/O D7 D8 D9 D20 P4 R4 T4 U4 AC7 AC8 AC9 AC20 AC21 AC22 Vcc SI/O D21 D22 D23 D24 E23 F23 R23 T23 AB24 AC23 AC24 Vcc Core D13 D14 D15 K4 L4 L23 M4 M23 N4 N23 P23 AC13 AC14 AC15 Table 21 RC32438 Power Pins Vcc PLL Y2, AA3 45 of 59 May 25, 2004 IDT 79RC32438 RC32438 Ground Pins Vss D4 D5 D6 D10 D11 D12 D16 D17 D18 D19 E4 F4 G4 G23 H4 H23 J4 J23 K10 K11 K12 K13 K14 K15 K16 K17 K23 Vss L10 L11 L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 Vss P13 P14 P15 P16 P17 R3 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 Table 22 RC32438 Ground Pins Vss U15 U16 U17 U23 V4 V23 W4 W23 Y4 Y23 AA4 AA23 AB4 AB23 AC4 AC5 AC6 AC10 AC11 AC12 AC16 AC17 AC18 AC19 Vss PLL AA1, AC1 46 of 59 May 25, 2004 IDT 79RC32438 RC32438 Alternate Signal Functions Pin A14 B13 B15 C16 N3 P1 P3 T2 V3 W1 GPIO GPIO[22] GPIO[23] GPIO[20] GPIO[21] GPIO[01] GPIO[00] GPIO[02] GPIO[03] GPIO[05] GPIO[04] Alternate MADDR[24] MADDR[25] MADDR[22] MADDR[23] U0SINP U0SOUT U0RIN U0DCDN U0DSRN U0DTRN Pin Y1 Y3 AA2 AB1 AB2 AB3 AC2 AC3 AD3 AD5 GPIO GPIO[06] GPIO[08] GPIO[07] GPIO[09] GPIO[14] GPIO[11] GPIO[10] GPIO[12] GPIO[15] GPIO[27] Alternate U0RTSN U1SOUT U0CTSN U1SINP DMAREQN[0] U1DSRN U1DTRN U1RTSN DMAREQN[1] PCIREQN[5] Pin AE2 AE3 AE4 AE5 AE9 AF1 AF2 AF3 AF5 GPIO GPIO[13] GPIO[18] GPIO[24] GPIO[26] GPIO[30] GPIO[16] GPIO[17] GPIO[19] GPIO[28] Alternate U1CTSN DMAFINN[0] PCIREQN[4] PCIGNTN[4] PCIMUINTN DMADONE[0] DMADONE[1] DMAFINN[1] PCIGNTN[5] Table 23 RC32438 Alternate Signal Functions RC32438 Signals Listed Alphabetically The following table lists the RC32438 pins in alphabetical order. Signal Name BDIRN BGN BOEN BRN BWEN[00] BWEN[01] CLK COLDRSTN CPU CSN[00] CSN[01] CSN[02] CSN[03] CSN[04] CSN[05] I/O Type O O O I O O I I O O O O O O O Location C9 B7 A7 C8 B6 A6 W3 C4 T3 C7 B5 A5 C6 B4 A4 Signal Category Memory and Peripheral Bus Memory and Peripheral Bus Memory and Peripheral Bus Memory and Peripheral Bus Memory and Peripheral Bus Memory and Peripheral Bus System System Debug Memory and Peripheral Bus Table 24 RC32438 Alphabetical Signal List (Part 1 of 9) 47 of 59 May 25, 2004 IDT 79RC32438 Signal Name DDRADDR[00] DDRADDR[01] DDRADDR[02] DDRADDR[03] DDRADDR[04] DDRADDR[05] DDRADDR[06] DDRADDR[07] DDRADDR[08] DDRADDR[09] DDRADDR[10] DDRADDR[11] DDRADDR[12] DDRADDR[13] DDRBA[00] DDRBA[01] DDRCASN DDRCKE DDRCKN[00] DDRCKN[01] DDRCKP[00] DDRCKP[01] DDRCSN[00] DDRCSN[01] DDRDATA[00] DDRDATA[01] DDRDATA[02] DDRDATA[03] DDRDATA[04] DDRDATA[05] DDRDATA[06] DDRDATA[07] DDRDATA[08] DDRDATA[09] DDRDATA[10] I/O Type O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location AC26 AB25 AB26 AA25 AA26 Y26 W25 W24 V24 U26 T25 U24 T26 R25 Y25 W26 V26 K26 H24 Y24 G24 AA24 T24 R26 C23 B23 A24 C24 A25 A26 B26 C26 C25 E24 D26 Signal Category DDR Bus Table 24 RC32438 Alphabetical Signal List (Part 2 of 9) 48 of 59 May 25, 2004 IDT 79RC32438 Signal Name DDRDATA[11] DDRDATA[12] DDRDATA[13] DDRDATA[14] DDRDATA[15] DDRDATA[16] DDRDATA[17] DDRDATA[18] DDRDATA[19] DDRDATA[20] DDRDATA[21] DDRDATA[22] DDRDATA[23] DDRDATA[24] DDRDATA[25] DDRDATA[26] DDRDATA[27] DDRDATA[28] DDRDATA[29] DDRDATA[30] DDRDATA[31] DDRDM[00] DDRDM[01] DDRDM[02] DDRDM[03] DDRDM[04] DDRDM[05] DDRDM[06] DDRDM[07] DDRDQS[00] DDRDQS[01] DDRDQS[02] DDRDQS[03] DDROEN[00] DDROEN[01] I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I/O I/O I/O I/O O O Location D25 E25 G26 F26 F25 G25 J24 H25 J26 K24 J25 L26 M24 L25 M26 N24 M25 N25 R24 P26 P25 B25 E26 L24 P24 AE26 AD24 AF25 AE25 B24 F24 K25 N26 AC25 AD26 Signal Category DDR Bus Table 24 RC32438 Alphabetical Signal List (Part 3 of 9) 49 of 59 May 25, 2004 IDT 79RC32438 Signal Name DDROEN[02] DDROEN[03] DDRRASN DDRVREF DDRWEN EJTAG_TMS EXTCLK GPIO[00] GPIO[01] GPIO[02] GPIO[03] GPIO[04] GPIO[05] GPIO[06] GPIO[07] GPIO[08] GPIO[09] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] I/O Type O O O I O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location AD25 AF26 V25 H26 U25 R2 C3 P1 N3 P3 T2 W1 V3 Y1 AA2 Y3 AB1 AC2 AB3 AC3 AE2 AB2 AD3 AF1 AF2 AE3 AF3 B15 C16 A14 B13 AE4 A2 AE5 AD5 EJTAG/ICE System General Purpose Input/Output Signal Category DDR Bus Table 24 RC32438 Alphabetical Signal List (Part 4 of 9) 50 of 59 May 25, 2004 IDT 79RC32438 Signal Name GPIO[28] GPIO[29] GPIO[30] GPIO[31] INST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MADDR[00] MADDR[01] MADDR[02] MADDR[03] MADDR[04] MADDR[05] MADDR[06] MADDR[07] MADDR[08] MADDR[09] MADDR[10] MADDR[11] MADDR[12] MADDR[13] MADDR[14] MADDR[15] MADDR[16] MADDR[17] MADDR[18] MADDR[19] MADDR[20] MADDR[21] MDATA[00] MDATA[01] I/O Type I/O I/O I/O I/O O I I O I I O O O O O O O O O O O O O O O O O O O O O O I/O I/O Location AF5 A13 AE9 A3 R1 U2 U1 U3 AD2 AD1 B22 C22 A22 B21 C21 A21 B20 A20 C20 B19 A19 C19 B18 A18 B17 C18 A17 B16 C17 A16 B14 A15 C15 C12 Memory and Peripheral Bus Debug EJTAG/ICE Signal Category General Purpose Input/Output Table 24 RC32438 Alphabetical Signal List (Part 5 of 9) 51 of 59 May 25, 2004 IDT 79RC32438 Signal Name MDATA[02] MDATA[03] MDATA[04] MDATA[05] MDATA[06] MDATA[07] MDATA[08] MDATA[09] MDATA[10] MDATA[11] MDATA[12] MDATA[13] MDATA[14] MDATA[15] MII0CL MII0CRS MII0RXCLK MII0RXD[00] MII0RXD[01] MII0RXD[02] MII0RXD[03] MII0RXDV MII0RXER MII0TXCLK MII0TXD[00] MII0TXD[01] MII0TXD[02] MII0TXD[03] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[00] MII1RXD[01] I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I O O O O O O I I I I I Location B12 B10 C14 C13 A12 A11 B11 C11 A10 B9 C10 B8 A9 A8 A1 B1 C2 C1 D2 D3 D1 G2 G1 G3 E2 E3 E1 F2 F3 F1 H2 H1 H3 J2 J1 Ethernet Interfaces Signal Category Memory and Peripheral Bus Table 24 RC32438 Alphabetical Signal List (Part 6 of 9) 52 of 59 May 25, 2004 IDT 79RC32438 Signal Name MII1RXD[02] MII1RXD[03] MII1RXDV MII1RXER MII1TXCLK MII1TXD[00] MII1TXD[01] MII1TXD[02] MII1TXD[03] MII1TXENP MII1TXER MIIMDC MIIMDIO OEN PCIAD[00] PCIAD[01] PCIAD[02] PCIAD[03] PCIAD[04] PCIAD[05] PCIAD[06] PCIAD[07] PCIAD[08] PCIAD[09] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] I/O Type I I I I I O O O O O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location K2 J3 K1 L2 K3 L1 M2 M1 L3 N2 N1 M3 P2 C5 AD22 AF23 AE23 AF22 AD23 AE22 AD20 AF21 AD19 AF20 AE20 AD18 AF19 AE19 AF18 AD17 AE12 AF11 AD10 AE11 AF10 Memory and Peripheral Bus PCI Bus Signal Category Ethernet Interfaces Table 24 RC32438 Alphabetical Signal List (Part 7 of 9) 53 of 59 May 25, 2004 IDT 79RC32438 Signal Name PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCICBEN[00] PCICBEN[01] PCICBEN[02] PCICBEN[03] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[00] PCIGNTN[01] PCIGNTN[02] PCIGNTN[03] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[00] PCIREQN[01] PCIREQN[02] PCIREQN[03] PCIRSTN PCISERRN PCISTOPN PCITRDYN RSTN RWN I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Location AD9 AE10 AF9 AF8 AE8 AD7 AF7 AE7 AF6 AD6 AE6 AE21 AE18 AF14 AD8 AD12 AE16 AE15 AD13 AE24 AF24 AD21 AD14 AE17 AF17 AD16 AF13 AD11 AE14 AF12 AE13 AF16 AD15 AF15 A23 B3 System Memory and Peripheral Bus Signal Category PCI Bus Table 24 RC32438 Alphabetical Signal List (Part 8 of 9) 54 of 59 May 25, 2004 IDT 79RC32438 Signal Name SCK SCL SDA SDI SDO Vcc CORE I/O Type I/O I/O I/O I/O I/O Location W2 AF4 AD4 V2 V1 D13, D14, D15, K4, L4, L23, M4, M23, N4, N23, P23, AC13, AC14, AC15 See Table 21 for a listing of power pins. SPI Interface Signal Category SPI Interface I2C Vcc I/O, Vcc SI/O Vcc PLL Vss Vss PLL WAITACKN I See Table 22 for a listing of ground pins. B2 Memory and Peripheral Bus Table 24 RC32438 Alphabetical Signal List (Part 9 of 9) 55 of 59 May 25, 2004 IDT 79RC32438 RC32438 Pinout -- Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Vss (Ground) Vcc SI/O (Power) Vcc I/O (Power) Vcc Core (Power) VssPLL VccPLL VccPLL 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VssPLL 56 of 59 May 25, 2004 IDT 79RC32438 RC32438 Package Drawing -- 416-pin BGA 57 of 59 May 25, 2004 IDT 79RC32438 RC32438 Package Drawing -- Page Two 58 of 59 May 25, 2004 IDT 79RC32438 Ordering Information 79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank I Commercial Temperature (0C to +70C Ambient) Industrial Temperature (-40 C to +85 C Ambient) 416-pin BGA 200 MHz Pipeline Clk 233 MHz Pipeline Clk 266 MHz Pipeline Clk 300 MHz Pipeline Clk Integrated Core Processor BB 200 233 266 300 438 K 79RC32 1.2V +/- 0.1V Core Voltage (200/233) 1.3V+/- 0.1V Core Voltage (266/300) 32-bit Embedded Microprocessor Valid Combinations 79RC32K438 -200BB, 233BB, 266BB, 300BB 79RC32K438 -200BBI, 233BBI 416-pin BGA package, Commercial Temperature 416-pin BGA package, Industrial Temperature CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com 59 of 59 for Tech Support: email: rischelp@idt.com phone: 408-492-8208 May 25, 2004 |
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